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w25q32v publication release date: august 19, 2009 - 1 - preliminary - revision e 32m-bit serial flash memory with dual and quad spi
w25q32v - 2 - table of contents 1. ............................................................................................................... 5 general description 2. ....................................................................................................................................... 5 features 3. ............................................................................................ 6 pin configuration soic 208-mil 4. ....................................................................... 6 pad configuration wson 6x5-mm / 8x6-mm 5. ............................................................. 6 pin description soic 208-mil, and wson 6x5-mm 6. ............................................................................................ 7 pin configuration soic 300-mil 7. .................................................................................................. 7 pin description soic 300-mil 7.1 ..................................................................................................................... 8 package types 7.2 .................................................................................................................. 8 chip select (/cs) 7.3 .................................... 8 serial data input, output and ios (di, do and io0, io1, io2, io3) 7.4 ............................................................................................................... 8 write protect (/wp) 7.5 ..................................................................................................................... 8 hold (/hold) 7.6 ................................................................................................................ 8 serial clock (clk) 8. ............................................................................................................................ 9 block diagram 9. ....................................................................................................... 10 functional description 9.1 ............................................................................................................. 10 spi operations 9.1.1 .....................................................................................................10 standard spi instructions 9.1.2 ............................................................................................................10 dual spi instructions 9.1.3 ...........................................................................................................10 quad spi instructions 9.1.4 .......................................................................................................................10 hold function 9.2 ....................................................................................................... 11 write protection 9.2.1 ..........................................................................................................11 write protect features 10. ........................................................................................ 12 control and status registers 10.1 .......................................................................................................... 12 status register 10.1.1 ............................................................................................................................... ...12 busy 10.1.2 ..................................................................................................12 write enable latch (wel) 10.1.3 ....................................................................................12 block protect bits (bp2, bp1, bp0) 10.1.4 ...........................................................................................12 top/bottom block protect (tb) 10.1.5 ................................................................................................12 sector/block protect (sec) 10.1.6 ...............................................................................13 status register protect (srp1, srp0) 10.1.7 ..............................................................................................................13 quad enable (qe) 10.1.8 .............................................................................................13 erase suspend status (sus) 10.1.9 ....................................................................................15 status register memory protection 10.2 ................................................................................................................. 16 instructions 10.2.1 ..............................................................................16 manufacturer and devi ce identification 10.2.2 ........................................................................................................17 instruction set table 1
w25q32v ........................................................................18 publ ication release date: august 19, 2009 - 3 - preliminary - revision e 10.2.3 instruction set table 2 (read instructions) 10.2.4 ..............................................................................................................19 write enable (06h) 10.2.5 .............................................................................................................19 write disable (04h) 10.2.6 .......................................20 read status register-1 (05h) and read status register-2 (35h) 10.2.7 ................................................................................................21 write status register (01h) 10.2.8 .................................................................................................................22 read data (03h) 10.2.9 .................................................................................................................23 fast read (0bh) 10.2.10 ...........................................................................................24 fast read dual output (3bh) 10.2.11 ..........................................................................................25 fast read quad output (6bh) 10.2.12 .................................................................................................26 fast read dual i/o (bbh) 10.2.13 ...............................................................................................28 fast read quad i/o (ebh) 10.2.14 .....................................................................................30 octal word read quad i/o (e3h) 10.2.15 .........................................................................................................32 page program (02h) 10.2.16 ......................................................................................33 quad input page program (32h) 10.2.17 ...........................................................................................................34 sector erase (20h) 10.2.18 ...................................................................................................35 32kb block erase (52h) 10.2.19 ...................................................................................................36 64kb block erase (d8h) 10.2.20 .....................................................................................................37 chip erase (c7h / 60h) 10.2.21 ........................................................................................................38 erase suspend (75h) 10.2.22 ........................................................................................................39 erase resume (7ah) 10.2.23 ............................................................................................................40 power-down (b9h) 10.2.24 ...........................................................................40 release power-down / device id (abh) 10.2.25 ...............................................................................42 read manufacturer / device id (90h) 10.2.26 .........................................................................................43 read unique id number (4bh) 10.2.27 ................................................................................................................44 jedec id (9fh) 10.2.28 ................................................................45 continuous read mode reset (ffh or ffffh) 11. .................................................................. 46 electrical characteris tics (preliminary) 11.1 ................................................................................................ 46 absolute maximum ratings 11.2 .............................................................................................................. 46 operating ranges 11.3 .................................................................... 47 power-up timing and write inhibit threshold 11.4 .............................................................................................. 48 dc electrical characteristics 11.5 ............................................................................................. 49 ac measurement conditions 11.6 .............................................................................................. 50 ac electrical characteristics 11.7 ................................................................................. 51 ac electrical characteristics (cont?d) 11.8 ........................................................................................................... 52 serial output timing 11.9 ........................................................................................................................ 52 input timing 11.10 ....................................................................................................................... 52 hold timing 12. .......................................................................................................... 53 package specification 12.1 ........................................................................... 53 8-pin soic 208-mil (package code ss)
w25q32v .................................................................. 54 - 4 - 12.2 8-contact 6x5mm wson (package code zp) 12.3 .................................................................. 56 8-contact 8x6mm wson (package code ze) 12.4 .......................................................................... 57 16-pin soic 300-mil (package code sf) 13. .......................................................................................................... 58 ordering information 13.1 ........................................................................ 59 valid part numbers and top side marking 14. ...................................................................................................................... 60 revision history revision history (cont) .................................................................................................................... 61
w25q32v publication release date: august 19, 2009 - 5 - preliminary - revision e 1. general description the w25q32v (32m-bit) serial flash memory provides a storage solution for systems with limited space, pins and power. the 25q series offers flexibilit y and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly from dual/quad spi (xip) and storing voice, text and data. the devices operate on a single 2.7v to 3.6v power supply with current consumption as low as 4ma active and 1a for powe r-down. all devices are offered in space-saving packages. the w25q32v array is organized into 16,384 progra mmable pages of 256-bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (sector erase), groups of 128 (32kb block erase), groups of 256 (64kb block erase) or the entire chip (chip erase). the w25q32v has 1,024 erasable sectors and 64 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w25q32v supports the standard serial peripheral interface (spi), and a dual/quad output as well as dual/quad i/o spi: serial clock, chip select, se rial data i/o0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold). spi clock frequencies of up to 80mhz are supported allowing equivalent clock rates of 160mhz for dual output and 320mhz for quad output when us ing the fast read dual/quad output instructions. these transfer rates can outperform standard asynch ronous 8 and 16-bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8-clocks of instruction- overhead to read a 24-bit address, allowing tr ue xip (execute in place) operation. a hold pin, write protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. additionally , the device supports jedec standard manufacturer and device identification with a 64-bit unique serial number. 2. features ? family of spiflash memories ? w25q32: 32m-bit / 4m-byte (4,194,304) ? 256-bytes per programmable page ? standard, dual or quad spi ? standard spi: clk, /cs, di, do, /wp, /hold ? dual spi: clk, /cs, io 0 , io 1 , /wp, /hold ? quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 ? highest performance serial flash ? up to 6x that of ordinary serial flash ? 80mhz clock operation ? 160mhz equivalent dual spi ? 320mhz equivalent quad spi ? 40mb/s continuous data transfer rate ? efficient ?continuous read mode? ? low instruction overhead ? as few as 8 clocks to address memory ? allows true xip (execute in place) operation ? outperforms x16 parallel flash ? low power, wide temperature range ? single 2.7 to 3.6v supply ? 4ma active current, <1a power-down (typ.) ? -40c to +85c operating range ? flexible architecture with 4kb sectors ? uniform sector erase (4k-bytes) ? block erase (32k and 64k-bytes) ? program one to 256 bytes ? more than 100,000 erase/write cycles ? more than 20-year data retention ? advanced security features ? software and hardware write-protect ? top or bottom, sector or block selection ? lock-down and otp protection (1) ? 64-bit unique id for each device (1) ? space efficient packaging ? 8-pin soic 208-mil ? 8-pad wson 6x5-mm / (2) 8x6-mm ? 16-pin soic 300-mil ? contact winbond for kgd and csp options (1) contact winbond for details (2) special order, contact winbond for more ordering information.
w25q32v - 6 - 3. pin configuration soic 208-mil figure 1a. w25q32v pin assignments, 8-pin soic 208-mil (package code ss) 4. pad configuration wson 6x5-mm / 8x6-mm figure 1b. w25q32v pad assignments, 8-pad wson (package code zp & ze) 5. pin description soic 208-mil, and wson 6x5-mm pin no. pin name i/o function 1 /cs i chip select input 2 do (io1) i/o data output (data input output 1)* 1 3 /wp (io2) i/o write protect input ( data input output 2)* 2 4 gnd ground 5 di (io0) i/o data input (data input output 0)* 1 6 clk i serial clock input 7 /hold (io3) i/o hold input (data input output 3)* 2 8 vcc power supply *1 io0 and io1 are used for standard and dual spi instructions *2 io0 ? io3 are used for quad spi instructions
w25q32v publication release date: august 19, 2009 - 7 - preliminary - revision e 6. pin configuration soic 300-mil figure 1c. w25q32v pin assignments, 16-pin soic 300-mil (package code sf) 7. pin description soic 300-mil pad no. pad name i/o function 1 /hold (io3) i/o hold input (data input output 3)* 2 2 vcc power supply 3 n/c no connect 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/o data output (data input output 1)* 1 9 /wp (io2) i/o write protect input (d ata input output 2)* 2 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di (io0) i/o data input (data input output 0)* 1 16 clk i serial clock input *1 io0 and io1 are used for standard and dual spi instructions *2 io0 ? io3 are used for quad spi instructions
w25q32v - 8 - 7.1 package types w25q32v is offered in an 8-pin plastic 208-mil width soic (package code ss) and both the 6x5-mm wson (package code zp) and the wson 8x6-mm (pa ckage code ze) as shown in figure 1a, and 1b, respectively. the w25q32v is also offered in a 16- pin plastic 300-mil width soic (package code sf) as shown in figure 1c. package diagrams and dimensions are illustrated at the end of this datasheet. 7.2 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do, or io0, io1, io2, io3) pins are at high impedance. when deselected, the devices power consum ption will be at standby levels unless an internal erase, program or status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and inst ructions can be written to and data read from the device. after power-up, /cs must transition from high to low befor e a new instruction will be accepted. the /cs input must track the vcc supply level at power-up (see ?write protection? and figure 29). if needed a pull-up resister on /cs can be used to accomplish this. 7.3 serial data input, output and ios (di, do and io0, io1, io2, io3) the w25q32v supports standard spi, dual spi and q uad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write instructions, addresse s or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge clk. dual and quad spi instruction use the bidirectional io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read dat a or status from the device on the falling edge of clk. quad spi instructions require the non-volatile q uad enable bit (qe) in status register-2 to be set. when qe=1 the /wp pin becomes io2 and /hold pin becomes io3. 7.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block pr otect (sec, tb, bp2, bp1 and bp0) bits and status register protect (srp) bits, a portion or the entir e memory array can be hardware protected. the /wp pin is active low. when the qe bit of status regist er-2 is set for quad i/o, the /wp pin (hardware write protect) function is not available since this pin is used for io2. see figure 1a, 1b, and 1c for the pin configuration of quad i/o operation. 7.5 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (don?t care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. the /hold pin is active low. when the qe bit of status register-2 is set for quad i/o, the /hold pin function is not available since this pin is used for io3. see figure 1a, 1b, and 1c for the pin configuration of quad i/o operation. 7.6 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi operations")
w25q32v publication release date: august 19, 2009 - 9 - preliminary - revision e 8. block diagram figure 2. w25q32v block diagram 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 20ff00h 20ffffh ? block 32 (64kb) ? 200000h 2000ffh ? ? ? 3fff00h 3fffffh ? block 63 (64kb) ? 3f0000h 3f00ffh column decode and 256-byte page buffer beginning page address ending page address w25q32 spi command & control logic byte address latch / counter status register write control logic page address latch / counter high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data write protect logic and row decode do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 20ff00h 20ffffh ? block 32 (64kb) ? 200000h 2000ffh ? ? ? 3fff00h 3fffffh ? block 63 (64kb) ? 3f0000h 3f00ffh column decode and 256-byte page buffer beginning page address ending page address w25q32 spi command & control logic byte address latch / counter status register write control logic page address latch / counter high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation write protect logic and row decode di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) data do (io 1 )
w25q32v - 10 - 9. functional description 9.1 spi operations 9.1.1 standard spi instructions the w25q32v is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) and serial data output (do). standard spi instructions use the di input pin to serially write in structions, addresses or data to the device on the rising edge of clk. the do output pin is used to read data or stat us from the device on the falling edge clk. spi bus operation modes 0 (0,0) and 3 (1,1) are s upported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for m ode 0 the clk signal is normally low on the falling and rising edges of /cs. for mode 3 the clk signal is normally high on the falling and rising edges of /cs. 9.1.2 dual spi instructions the w25q32v supports dual spi operation when usi ng the "fast read dual output and dual i/o" (3b and bb hex) instructions. these instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devic es. the dual read instructions are ideal for quickly downloading code to ram upon power-up (code-shadowing) or for executing non-speed-critical code directly from the spi bus (xip ). when using dual spi instruct ions the di and do pins become bidirectional i/o pins: io0 and io1. 9.1.3 quad spi instructions the w25q32v supports quad spi operation when usi ng the "fast read quad output, fast read quad i/o and octal word read quad i/o" (6b, eb and e3 hex re spectively). these instructions allow data to be transferred to or from the device four to six time s the rate of ordinary serial flash. the quad read instructions offer a significant improvement in c ontinuous and random access transfer rates allowing fast code-shadowing to ram or execution directly from t he spi bus (xip). when using quad spi instructions the di and do pins become bidirectional io0 and io1, and the /wp and /hold pins become io2 and io3 respectively. quad spi instructions require the non-vola tile quad enable bit (qe) in status register-2 to be set. 9.1.4 hold function the /hold signal allows the w25q32v operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where t he spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. the /hold function is only available for standard spi and dual spi operation, not during quad spi. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already lo w. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data input (di) and serial clock (clk) are ignored. the chip select (/cs) signal should be kept acti ve (low) for the full duration of the /hold operation to avoid resetting the internal logi c state of the device.
w25q32v publication release date: august 19, 2009 - 11 - preliminary - revision e 9.2 write protection applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise dat a integrity. to address this concern the w25q32v provides several means to protec t data from inadvertent writes. 9.2.1 write protect features ? device resets when vcc is below threshold ? time delay write disable after power-up ? write enable/disable instructions and automat ic write disable after program and erase ? software and hardware (/wp pin) write protection using status register ? write protection using power-down instruction ? lock down write protection until next power-up (1) ? one time program (otp) write protection (1) note 1: these features are available upon specia l order. please contact winbond for details. upon power-up or at power-down, the w25q32v will ma intain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figure 29). while reset, all operations are disabled and no instructions are re cognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector eras e, block erase, chip erase and the write status register instructions. note that the chip select pi n (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull-up resister on /cs can be used to accomplish this. after power-up the device is automatically placed in a write-disabled state with the status register write enable latch (wel) set to a 0. a write enable inst ruction must be issued before a page program, sector erase, chip erase or write status register inst ruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write stat us register instruction and setting the status register protect (srp 0, srp1) and block protect (sec,t b, bp2, bp1 and bp0) bits. these settings allow a portion or all of the memory to be configured as read only. used in conjunction with the write protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. see status register for further information. additionally, t he power-down instruction offers an extra level of write protection as all instructi ons are ignored except for the release power-down instruction.
w25q32v - 12 - 10. control and status registers the read status register-1 and stat us register-2 instructions can be used to provide status on the availability of the flash memory array, if the dev ice is write enabled or dis abled, the state of write protection and the quad spi setting. the write status register instruction can be used to configure the devices write protection features and quad spi setting. write access to the status register is controlled by the state of the non-volatile status register protect bits (srp0, srp1), the wri te enable instruction, and in some cases the /wp pin. 10.1 status register 10.1.1 busy busy is a read only bit in the status register (s0) t hat is set to a 1 state w hen the device is executing a page program, sector erase, block er ase, chip erase or write status register instruction. during this time the device will ignore further instructions ex cept for the read status register and erase suspend instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when t he program, erase or write status register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 10.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the wel status bit is cleared to a 0 when the device is write disabled. a write disable state occurs upon power-up or after any of the following instructions: write disable, page program, sector erase, block erase, ch ip erase and write status register. 10.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0 ) are non-volatile read/write bits in the status register (s4, s3, and s2) that provide write protection c ontrol and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. 10.1.4 top/bottom block protect (tb) the non-volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as show n in the status register memory protection table. the factory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 10.1.5 sector/block protect (sec) the non-volatile sector protect bit (sec) controls if the block protec t bits (bp2, bp1, bp0) protect 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protec tion table. the default setting is sec=0.
w25q32v publication release date: august 19, 2009 - 13 - preliminary - revision e 10.1.6 status register protect (srp1, srp0) the status register protect bits (srp1 and srp0) are non- volatile read/write bits in the status register (s8 and s7). the srp bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (otp) protection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the stat us register can be written to after a write enable instruction, wel=1. [factory default] 0 1 0 hardware protected when /wp pin is low the status register locked and can not be written to. 0 1 1 hardware unprotected when /wp pin is high the status register is unlocked and can be written to after a write e nable instruction, wel=1. 1 0 x power supply lock-down (1) status register is protect ed and can not be written to again until the next power-down, power-up cycle. (2) 1 1 x one time program (1) status register is permanently protected and can not be written to. note: 1. these features are available upon special order. please contact winbond for details. 2. when srp1, srp0 = (1, 0), a power-down, power- up cycle will change srp1, srp0 to (0, 0) state. 10.1.7 quad enable (qe) the quad enable (qe) bit is a non-volatile read/write bi t in the status register (s9) that allows quad operation. when the qe bit is set to a 0 state (f actory default) the /wp pin and /hold are enabled. when the qe bit is set to a 1 the quad io2 and io3 pins are enabled. warning: the qe bit should never be set to a 1 dur ing standard spi or dual spi operation if the /wp or /hold pins are tied directly to the power supply or ground. 10.1.8 erase suspend status (sus) the suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase suspend (75h) instruction. the sus status bit is cleared to 0 by the erase resume (7ah) instruction as well as a power-down, power-up cycle.
w25q32v - 14 - s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non-volatile) sector protect (non-volatile) top/bottom protect (non-volatile) block protect bits (non-volatile) write enable latch erase/write in progress s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non-volatile) sector protect (non-volatile) top/bottom protect (non-volatile) block protect bits (non-volatile) write enable latch erase/write in progress figure 3a. status register-1 s15 s14 s13 s12 s11 s10 s9 s8 sus (r) (r) (r) (r) (r) qe srp1 suspend status reserved quad enable (non-volatile) status register protect 1 ( non-volatile ) s15 s14 s13 s12 s11 s10 s9 s8 sus (r) (r) (r) (r) (r) qe srp1 suspend status reserved quad enable (non-volatile) status register protect 1 ) ( non-volatile figure 3b. status register-2
w25q32v publication release date: august 19, 2009 - 15 - preliminary - revision e 1 0.1.9 s tatus register memory protection status register (1) w25q32v (32m-bit) memory protection sec tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 0 none none none none 0 0 0 0 1 63 3f0000h - 3fffffh 64kb upper 1/64 0 0 0 1 0 62 and 63 3e0000h - 3fffffh 128kb upper 1/32 0 0 0 1 1 60 thru 63 3c0000h - 3fffffh 256kb upper 1/16 0 0 1 0 0 56 thru 63 380000h - 3fffffh 512kb upper 1/8 0 0 1 0 1 48 thru 63 300000h - 3fffffh 1mb upper 1/4 0 0 1 1 0 32 thru 63 200000h - 3fffffh 2mb upper 1/2 0 1 0 0 1 0 000000h - 00ffffh 64kb lower 1/64 0 1 0 1 0 0 and 1 000000h - 01ffffh 128kb lower 1/32 0 1 0 1 1 0 thru 3 000000h - 03ffffh 256kb lower 1/16 0 1 1 0 0 0 thru 7 000000h - 07ffffh 512kb lower 1/8 0 1 1 0 1 0 thru 15 000000h ? 0fffffh 1mb lower 1/4 0 1 1 1 0 0 thru 31 000000h ? 1fffffh 2mb lower 1/2 x x 1 1 1 0 thru 63 000000h ? 3fffffh 4mb all 1 0 0 0 1 63 3ff000h ? 3fffffh 4kb top block 1 0 0 1 0 63 3fe000h ? 3fffffh 8kb top block 1 0 0 1 1 63 3fc000h ? 3fffffh 16kb top block 1 0 1 0 x 63 3f8000h ? 3fffffh 32kb top block 1 1 0 0 1 0 000000h ? 000fffh 4kb bottom block 1 1 0 1 0 0 000000h ? 001fffh 8kb bottom block 1 1 0 1 1 0 000000h ? 003fffh 16kb bottom block 1 1 1 0 x 0 000000h ? 007fffh 32kb bottom block note: 1. x = don?t care
w25q32v - 16 - 10.2 instructions the instruction set of the w25q32v consists of twenty seven basic instructions that are fully controlled through the spi bus (see instruction set table). instru ctions are initiated with the falling edge of chip select (/cs). the first byte of data clocked into the di input provides the instruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and ma y be followed by address bytes, data bytes, dummy bytes (don?t care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diagram s for each instruction are included in figures 4 through 30. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (/cs driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. this feature further protects the device from inadvertent writes. additionally, wh ile the memory is being programmed or erased, or when the status register is being written, all inst ructions except for read status r egister will be ignored until the program or erase cycle has completed. 10.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h 9fh w25q32 15h 4016h
w25q32v publication release date: august 19, 2009 - 17 - preliminary - revision e 10.2.2 instruction set table 1 (1 ) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 write enable 06h write disable 04h read status register-1 05h (s7?s0) (2) read status register-2 35h (s15-s8) (2) write status register 01h (s7?s0) (s15-s8) page program 02h a23?a16 a15?a8 a7?a0 (d7?d0) quad page program 32h a23?a16 a15?a8 a7?a0 (d7?d0, ?) (3) block erase (64kb) d8h a23?a16 a15?a8 a7?a0 block erase (32kb) 52h a23?a16 a15?a8 a7?a0 sector erase (4kb) 20h a23?a16 a15?a8 a7?a0 chip erase c7h/60h erase suspend 75h erase resume 7ah power-down b9h continuous read mode reset (4) ffh ffh release power down / device id abh dummy dummy dummy (id7-id0) (5) manufacturer/ device id (6) 90h dummy dummy 00h (mf7-mf0) (id7-id0) read unique id (7) 4bh dummy dummy dummy dummy (id63-id0) jedec id 9fh (mf7-mf0) manufacturer (id15-id8) memory type (id7-id0) capacity notes: 1. data bytes are shifted with most si gnificant bit first. byte fields with dat a in parenthesis ?()? indicate data being read from the device on the do pin. 2. the status register content s will repeat continuously until /c s terminates the instruction. 3. quad page program input data io0 = (d4, d0, ??) io1 = (d5, d1, ??) io2 = (d6, d2, ??) io3 = (d7, d3, ??) 4. this instruction is recommended w hen using the dual or quad ?continuous read mode? feature. see section 10.2.28 for more information. 5. the device id will repeat continuously until /cs terminates the instruction. 6. see manufacturer and devi ce identification table for device id information. 7. this feature is ava ilable upon special order. please contact winbond for details.
w25q32v - 18 - 10.2.3 instruction set table 2 (read instructions) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) fast read dual output 3bh a23-a16 a15-a8 a7-a0 dummy (d7-d0, ?) (1) fast read dual i/o bbh a23-a8 (2) a7-a0, m7-m0 (2) (d7-d0, ?) (1) fast read quad output 6bh a23-a16 a15-a8 a7-a0 dummy (d7-d0, ?) (3) fast read quad i/o ebh a23-a0, m7-m0 (4) (x,x,x,x, d7-d0, ?) (5) (d7-d0, ?) (3) octal word read quad i/o (6) e3h a23-a0, m7-m0 (4) (d7-d0, ?) (3) notes: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a 10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a 11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ?..) io1 = (d5, d1, ?..) io2 = (d6, d2, ?..) io3 = (d7, d3, ?..) 4. quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast read quad i/o data io0 = (x, x, x, x, d4, d0, ?..) io1 = (x, x, x, x, d5, d1, ?..) io2 = (x, x, x, x, d6, d2, ?..) io3 = (x, x, x, x, d7, d3, ?..) 6. the lowest 4 address bits must be 0. ( a0, a1, a2, a3 = 0 )
w25q32v publication release date: august 19, 2009 - 19 - preliminary - revision e 10.2.4 write enable (06h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in t he status register to a 1. the wel bit must be set prior to every page pr ogram, sector erase, block erase, chip erase and write status register instruction. the write enable instruction is enter ed by driving /cs low, shifting the instruction code ?06h? into the data input (di) pi n on the rising edge of clk, and then driving /cs high. figure 4. write enable instruction sequence diagram 10.2.5 write disable (04h) the write disable instruction (figure 5) resets the wri te enable latch (wel) bit in the status register to a 0. the write disable instru ction is entered by driving /cs low, shifting the instruction code ?04h? into the di pin and then driving /cs high. no te that the wel bit is automatically reset after power-up and upon completion of the write status register, page pr ogram, sector erase, block erase and chip erase instructions. figure 5. write disable in struction sequence diagram
w25q32v - 20 - 10.2.6 read status register-1 (05h) and read status register-2 (35h) the read status register instructi ons allow the 8-bit status register s to be read. the instruction is entered by driving /cs low and shifting the instructi on code ?05h? for status register-1 and ?35h? for status register-2 into the di pin on the rising edge of clk. the status r egister bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. the status register bits are shown in figure 3a and 3b and include the busy, wel, bp2-bp0, tb, sec, srp0, srp1, qe and sus bits (see description of the st atus register earlier in this datasheet). the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the st atus register can be read continuously, as shown in figure 6. the inst ruction is completed by driving /cs high. figure 6. read status register instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 21 - preliminary - revision e 10.2.7 write status register (01h) the write status register instruction allows the status register to be written. a write enable instruction must previously have been exec uted for the device to accept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is enter ed by driving /cs low, sending the instruction code ?01h?, and t hen writing the status register data byte as illustrated in figure 7. the status register bits are shown in fi gure 3 and described earlier in this datasheet. only non-volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (b its 7, 5, 4, 3, 2 of status register-1) and qe, srp1(bits 9 and 8 of status regist er-2) can be written to. all other status register bit locations are read-only and will not be affected by the write status r egister instruction. the /cs pin must be driven high after the eighth or sixt eenth bit of data that is clocked in. if this is not done the write status register instru ction will not be executed. if /cs is driven high after the eighth clock (compatible with the 25x series) the qe and srp1 bits will be cleared to 0. after /cs is driven high, the self-timed write status r egister cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progre ss, the read status regist er instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write register cycle has finished the write enable latch (wel) bit in the status register will be cleared to 0. the write status register instru ction allows the block protect bits (sec, tb, bp2, bp1 and bp0) to be set for protecting all, a portion, or none of the memo ry from erase and program instructions. protected areas become read-only (see status register memory protection table and description). the write status register instruction also allows t he status register protect bits (srp 0, srp1) to be set. those bits are used in conjunction with the write protect (/wp) pin, lock out or otp features to disable writes to the status register. please refer to 10.1.6 for detail ed descriptions regarding status register protection methods. factory default for all status register bits are 0. figure 7. write status register instruction sequence diagram
w25q32v - 22 - 10.2.8 read data (03h) the read data instruction allows one more data by tes to be sequentially read from the memory. the instruction is initiated by drivi ng the /cs pin low and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the di pin. the c ode and address bits are latched on the rising edge of the clk pin. after the address is receiv ed, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most signi ficant bit (msb) first. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figur e 8. if a read data instruction is issued while an erase, program or write cycle is in process (bu sy=1) the instruction is ignored and will not have any effects on the current cycle. the r ead data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 8. read data instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 23 - preliminary - revision e 10.2.9 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics) . this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 9. the dummy clocks allow the devices internal circuits additional time for setting up the in itial address. during the du mmy clocks the data value on the do pin is a ?don?t care?. figure 9. fast read instruction sequence diagram
w25q32v - 24 - ution. 10.2.10 fast read dual output (3bh) the fast read dual output (3bh) in struction is similar to the standard fast read (0bh) instruction except that data is output on two pins; io 0 and io 1 . this allows data to be transferred from the w25q32v at twice the rate of standard spi devices. the fast r ead dual output instruction is ideal for quickly downloading code from flash to ram upon power-up or for applications that cache code-segments to ram for exec similar to the fast read instructi on, the fast read dual output in struction can operate at the highest possible frequency of f r (see ac electrical characteristics) . this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 10. the dummy clocks allow the device's internal circuits additional time for setting up the in itial address. the input dat a during the dummy clocks is ?don?t care?. however, the io 0 pin should be high-impedance prior to the falling edge of the first data out clock. figure 10. fast read dual output instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 25 - preliminary - revision e 10.2.11 fast read quad output (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . a quad enable of status register-2 must be executed before the device will acc ept the fast read quad output inst ruction (status register bit qe must equal 1). the fast read quad output instructi on allows data to be transferred from the w25q32v at four times the rate of standard spi devices. the fast read quad output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 11. the dummy clocks allow the dev ice's internal circuits additional time for setting up the initial address. the input data dur ing the dummy clocks is ?don?t care?. however, the io pins should be high-impedance prior to the falling edge of the first data out clock. figure 11. fast read quad output instruction sequence diagram
w25q32v - 26 - 10.2.12 fast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23-0) two bits per clock. this reduced instruction overhead may allow for code execution (xip) directly from the dual spi in some applications. fast read dual i/o with ?continuous read mode? the fast read dual i/o instruction can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 12a. the upper nibble of the (m7-4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). however, the io pins should be high-impedance prio r to the falling edge of the first data out clock. if the ?continuous read mode? bits (m7-0) equals ?ax? hex, then the next fast read dual i/o instruction (after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 12b. this reduces the instruction sequence by eight cl ocks and allows the read address to be immediately entered after /cs is asserted low. if the ?continuous read mode? bits (m7-0) are any value other than ?ax? hex, the next instruction (after /cs is raised and t hen lowered) requires the first byte instruction code, thus returning to normal operation. a ?continuous read mode? reset instruction can be used to reset (m7-0) before issuing normal instructions (see 10.2.28 for detailed descriptions). figure 12a. fast read dual input/output instruct ion sequence diagram (m7-0 = 0xh or not axh)
w25q32v publication release date: august 19, 2009 - 27 - preliminary - revision e figure 12b. fast read dual input/output in struction sequence diagram (m7-0 = axh)
w25q32v - 28 - 10.2.13 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy clock are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip ) directly from the quad spi. the quad enable bit (qe) of status register-2 must be set to enable the fast read quad i/o instruction. fast read quad i/o with ?continuous read mode? the fast read quad i/o instruction can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 13a. the upper nibble of the (m7-4) controls the length of the next fast r ead quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). however, the io pins should be high-impedance prio r to the falling edge of the first data out clock. if the ?continuous read mode? bits (m7-0) equals ?ax? hex, then the next fast read quad i/o instruction (after /cs is raised and then lowered) does not require the ebh instruction code, as shown in figure 13b. this reduces the instruction sequence by eight cl ocks and allows the read address to be immediately entered after /cs is asserted low. if the ?continuous read mode? bits (m7-0) are any value other than ?ax? hex, the next instruction (after /cs is raised and t hen lowered) requires the first byte instruction code, thus returning to normal operation. a ?continuous read mode? reset instruction can be used to reset (m7-0) before issuing normal instructions (see 10.2.29 for detailed descriptions). byte 1 byte 2 byte 1 byte 2 figure 13a. fast read quad input/output instruct ion sequence diagram (m7-0 = 0xh or not axh)
w25q32v publication release date: august 19, 2009 - 29 - preliminary - revision e figure 13b. fast read quad input/output in struction sequence diagram (m7-0 = axh)
w25q32v - 30 - 10.2.14 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is si milar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1, a2, a3) must equal 0. as a result, the four dummy clocks are not required, which further reduces the instru ction overhead allowing even faster random access for code execution (xip). the quad enabl e bit (qe) of status register-2 must be set to enable the octal word read quad i/o instruction. octal word read quad i/o with ?continuous read mode? the octal word read quad i/o instruction can fu rther reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 14a. the upper nibble of the (m7-4) controls the length of the next octal word read quad i/o instruction through the inclusion or exclusion of the fi rst byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). however, the io pins should be high-im pedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits (m7-0) equals ?a x? hex, then the next octal word read quad i/o instruction (after /cs is raised and then lowered) does not require the e3h instru ction code, as shown in figure 14b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if t he ?continuous read mode? bits (m7-0) are any value other than ?ax? hex, the next instruction (after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operati on. a ?continuous read mode? reset instruction can be used to reset (m7-0) before issuing normal inst ructions (see 10.2.28 for detailed descriptions). instruction (e3h) byte 1 byte 2 byte 3 figure 14a. octal word read quad i/o instru ction sequence (m7-0 = 0xh or not axh) 4040 40 5151 51 6262 62 7373 73 40 51 62 73 byte 4 instruction (e3h) byte 1 byte 2 byte 3 404040 40 4040 515151 51 5151 626262 62 6262 737373 73 7373 4040 5151 6262 7373 byte 4
w25q32v publication release date: august 19, 2009 - 31 - preliminary - revision e byte 1 4 0 5 1 6 2 7 3 figure 14b. octal word read quad i/o instruction sequence (m7-0 = axh) byte 2 byte 3 byte 4 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 byte 1 4 0 4 0 5 1 5 1 6 2 6 2 7 3 7 3 byte 2 byte 3 by te 4 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3
w25q32v - 32 - 10.2.15 page program (02h) the page program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program in struction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 15. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any e ffect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page progr am instruction will not be executed. after /cs is driven high, the self-timed page progr am instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and t he device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (we l) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits. figure 15. page program instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 33 - preliminary - revision e 10.2.16 quad input page program (32h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applic ations that have slow clock speeds <5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock-in the data. to use quad page program the quad enable in status register-2 must be set (qe=1). a write enable instruction must be executed befor e the device will accept the quad page program instruction (status register-1, wel=1). the instructi on is initiated by driving the /cs pin low then shifting the instruction code ?32h? followed by a 24-bit address (a23-a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instruction while data is bei ng sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 16. figure 16. quad input page program instruction sequence diagram
w25q32v - 34 - 10.2.17 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be exec uted before the device will a ccept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?20h? followed a 24-bit sector address (a23-a0) (see figure 2). the sector erase instruction sequence is shown in figure 17. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read stat us register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other inst ructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the stat us register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 17. sector erase instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 35 - preliminary - revision e 10.2.18 32kb block erase (52h) the block erase instruction sets all memory within a specified block (32k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be exec uted before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?52h? followed a 24- bit block address (a23-a0) (see figure 2). the block erase instruction sequence is shown in figure 18. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read stat us register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the blo ck erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other in structions again. after t he block erase cycle has finished the write enable latch (wel) bit in the st atus register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 18. 32kb block erase instruction sequence diagram
w25q32v - 36 - 10.2.19 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be exec uted before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?d8h? followed a 24- bit block address (a23-a0) (see figure 2). the block erase instruction sequence is shown in figure 19. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status r egister instruction may still be access ed for checking the status of the busy bit. the busy bit is a 1 during the block eras e cycle and becomes a 0 when the cycle is finished and the device is ready to accept ot her instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is pr otected by the block protect ( sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 19. 64kb block erase instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 37 - preliminary - revision e 10.2.20 chip erase (c7h / 60h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?c7h? or ?60h?. the chip eras e instruction sequence is shown in figure 20. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driv en high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be a ccessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and bec omes a 0 when finished and the device is ready to accept other instructions again. a fter the chip erase cycle has finis hed the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be exec uted if any section of the array is protected by the block pr otect (bp2, bp1, and bp0) bits (see st atus register memory protection table). figure 20. chip erase instruction sequence diagram
w25q32v - 38 - 10.2.21 erase suspend (75h) the erase suspend instruction ?75h?, allows the system to interrupt a sector or block erase operation and then read from or program data to, any other se ctors or blocks. the erase suspend instruction sequence is shown in figure 21. the write status register instruction (01h) and erase instructions (20h, 52h, d8h, c7h, 60h) are not allowed during erase suspend. erase suspend is valid only during the sector or block erase operation. if written during the chip erase or program operation, the erase suspend instruction is ignored. the erase suspend instruction ?75h? will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase is on-going. if the sus bit equals to 1 or the busy bit equals to 0, the su spend instruction will be ignored by the device. a maximum of time of ?t sus ? (see ac characteristics) is requir ed to suspend the erase operation. the busy bit in the status register will be cleared from 1 to 0 within ?t sus ? and the sus bit in the status register will be set from 0 to 1 immediately afte r erase suspend. for a previously resumed erase operation, it is also required that the suspend inst ruction ?75h? is not issued earlier than a minimum of time of ?t sus ? following the preceding resume instruction ?7ah?. unexpected power off during the erase suspend st ate will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the sect or or block that was being suspended may become corrupted. it is recommended for the user to implement system design techniques against the accidental power interrupti on and preserve data integrity during erase suspend state. figure 21. erase suspend instruction sequence
w25q32v publication release date: august 19, 2009 - 39 - preliminary - revision e 10.2.22 erase resume (7ah) the erase resume instruction ?7ah? must be written to resume the sector or block erase operation after an erase suspend. the resume instruction ?7ah? will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation. if the sus bit equals to 0 or the busy bit equals to 1, the resume instruction ?7ah? will be ignored by the device. the erase resume instruction sequence is shown in figure 22. resume instruction is ignored if the previous erase suspend operation was interrupted by unexpected power off. it is also required that a subsequent er ase suspend instruction not to be issued within a minimum of time of ?t sus ? following a previous resume instruction. figure 22. erase resume instruction sequence
w25q32v - 40 - 10.2.23 power-down (b9h) although the standby current during nor mal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery powered applic ations (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 23. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the power-down instruction will not be executed. afte r /cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the pow er-down state only the release from power- down / device id instruction, which restores the dev ice to normal operation, will be recognized. all other instructions are ignored. this incl udes the read status register instru ction, which is always available during normal operation. ignoring all but one instructi on makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with the standby current of icc1. figure 23. deep power-down instruction sequence diagram 10.2.24 release power-down / device id (abh) the release from power-down / device id instructi on is a multi-purpose instruction. it can be used to release the device from the power-down or obtain the devices electronic identification (id) number. to release the device from the powe r-down, the instruction is issued by driving the /cs pin low, shifting the instruction code ?abh? and driving /cs high as shown in figure 24a. release from power-down will take the time duration of t res1 (see ac characteristics) before the device will resume normal operation and other instructions are accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in t he power-down state, the inst ruction is initiated by driving the /cs pin low and shifting the instruction c ode ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure
w25q32v 24b. the device id values for the w25q32v is listed in manufacturer and device identification table. the device id can be read continuously. the instru ction is completed by driving /cs high. when used to release the device from the power-down state and obtain the device id, the instruction is the same as previously described, and shown in figure 24b, except that after /c s is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions w ill be accepted. if the release from power-down / device id instruction is issued while an erase, pr ogram or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 24a. release power-down instruction sequence figure 24b. release power-down / devi ce id instruction sequence diagram publ ication release date: august 19, 2009 - 41 - preliminary - revision e
w25q32v - 42 - 10.2.25 read manufacturer / device id (90h) the read manufacturer/device id instruction is an al ternative to the release from power-down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is in itiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. afte r which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of cl k with most significant bit (msb) first as shown in figure 25. the device id values for the w25q32v is listed in manufacturer and device identification table. if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device id s can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 25. read manufacturer / device id diagram
w25q32v publication release date: august 19, 2009 - 43 - preliminary - revision e 10.2.26 read unique id number (4bh) the read unique id number instruction accesses a fa ctory-set read-only 64-bit number that is unique to each w25q32v device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a syst em. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code ?4bh? followed by a four bytes of dummy cl ocks. after which, the 64- bit id is shifted out on the falling edge of clk as shown in figure 26. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 101 102 103 do 63 62 61 60 59 2 1 0 * *=msb do 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 101 102 103 do 63 62 61 60 59 2 1 0 * *=msb do figure 26. read unique id number instruction sequence
w25q32v - 44 - 10.2.27 jedec id (9fh) for compatibility reasons, the w25q32v provides seve ral instructions to electronically determine the identity of the device. the read je dec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. t he instruction is initiated by driving the /cs pin low and shifting the instruction code ?9fh?. the je dec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) ar e then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 27. for memory type and capacity values refer to manufacture r and device identification table. figure 27. read jedec id instruction sequence diagram
w25q32v publication release date: august 19, 2009 - 45 - preliminary - revision e 10.2.28 continuous read mode reset (ffh or ffffh) for fast read dual/quad i/o operations, ?continuous read mode? bits (m7-0) are implemented to further reduce instruction overhead. by setting the (m7-0) to ?ax? hex, the next fast read dual/quad i/o operation does not require the bbh/ebh instructi on code (see 10.2.12 fast read dual i/o and 10.2.13 fast read quad i/o for detail descriptions). if the system controller is reset during operation it will likely send a standard spi instruction, such as read id (9fh) or fast read (0bh), to the w 25q32. however, as with most spi serial flash memories, the w25q32v does not have a hardware rese t pin, so if continuous read mode bits are set to ?ax? hex, the 25q16 will not rec ognize any standard spi instructions. to address this possibility, it is recommended to issue a continuous read mode reset instru ction as the first instruction after a system reset. doing so will release the continuous read m ode from the ?ax? hex state and allow standard spi instructions to be recognized. the continuous r ead mode reset instruction is shown in figure 28. /cs mode 0 mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 0 mode 3 clk io 0 io 1 io 2 io 3 mode bit reset for quad i/o mode bit reset for dual i/o don?t care don?t care don?t care ffh ffh /cs mode 0 mode 3 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 mode 0 mode 3 clk io 0 io 1 io 2 io 3 mode bit reset for quad i/o mode bit reset for dual i/o don?t care don?t care don?t care ffh ffh figure 28. continuous read mode reset for fast read dual/quad i/o to reset ?continuous read mode? during quad i/o operation, only eight clocks are needed. the instruction is ?ffh?. to reset ?continuous read mode? during dual i/o operation, sixteen clocks are needed to shift in instruction ?ffffh?.
w25q32v - 46 - 11. electrical characteristics (preliminary) (4) 11.1 absolute maximum ratings (1) parameters symbol conditions range unit supply voltage vcc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to vcc+0.4 v transient voltage on any pin v iot <20ns transient relative to ground ?2.0v to vcc+2.0v v storage temperature t stg ?65 to +150 c lead temperature t lead see note (2) c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v notes: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absol ute maximum ratings may affect device reliability. exposure beyond absolute maximum ra tings may cause permanent damage. 2. compliant with jedec standard j-std-20c for sm all body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1= 100pf, r1=1500 ohms, r2=500 ohms). 4. see preliminary designation at the end of this datasheet. 11.2 operating ranges spec parameter symbol conditions min max unit supply voltage (1) vcc f r = 80mhz, f r = 40mhz 2.7 3.6 v ambient temperature, operating t a industrial ?40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q32v publication release date: august 19, 2009 - 47 - preliminary - revision e 11.3 power-up timing and write inhibit threshold spec parameter symbol min max unit vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. figure 29. power-up timing and voltage levels
w25q32v - 48 - 11.4 dc electrical characteristics spec parameter symbol conditions min typ max unit input capacitance c in (1) v in = 0v (2) 6 pf output capacitance cout (1) v out = 0v (2) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc 1 5 a current read data / dual /quad 1mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 4/5/6 6/7.5/9 ma current read data / dual /quad 33mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 6/7/8 9/10.5/12 ma current read data / dual /quad 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 7/8/9 10/12/13.5 ma current read data / dual output read/quad output read 80mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 10/11/12 15/16.5/18 ma current write status register i cc 4 /cs = vcc 8 12 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il ?0.5 vcc x 0.3 v input high voltage v ih vcc x 0.7 vcc + 0.4 v output low voltage v ol i ol = 1.6 ma 0.4 v output high voltage v oh i oh = ?100 a vcc ? 0.2 v notes: 1. tested on sample basis and specified through desi gn and characterization data. ta=25 c, vcc 3v. 2. checker board pattern.
w25q32v publication release date: august 19, 2009 - 49 - preliminary - revision e 11.5 ac measurement conditions spec parameter symbol min max unit load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hi-z is defined as the point where data out is no longer driven. figure 30. ac measurement i/o waveform
w25q32v - 50 - 11.6 ac electrical characteristics spec description symbol alt min typ max unit clock frequency for instructions, except read data (03h) / octal word fast read (e3h) 2.7v-3.6v vcc & industrial temperature f r f c d.c. 80 mhz clock freq. read data (03h) and octal word fast read (e3h) instruction f r d.c. 40 mhz clock high, low time except read data (03h) t clh , t cll (1) 5.5 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read ? array read / erase or program ? read status registers) t shsl t csh 10/50 ns output disable time t shqz (2) t dis 7 ns clock low to output valid 2.7v-3.6v / 3.0v-3.6v t clqv 1 t v 1 7 / 6 ns clock low to output valid (for read id instructions) 2.7v-3.6v / 3.0v-3.6v t clqv 2 t v 2 8.5 / 7.5 ns output hold time t clqx t ho 0 ns /hold active setup time relative to clk t hlch 5 ns continued ? next page
w25q32v publication release date: august 19, 2009 - 51 - preliminary - revision e 11.7 ac electrical characteristics ( cont?d) spec description symbol alt min typ max unit /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s /cs high to next instruction after suspend t sus (2) 20 s write status register time t w 10 15 ms byte program time (first byte) (4) t bp1 30 50 s additional byte program time (after first byte) (4) t bp2 6 12 s page program time t pp 1.5 3 ms sector erase time (4kb) t se 120 200 ms block erase time (32kb) t be 1 0.3 0.7 s block erase time (64kb) t be 2 0.5 1 s chip erase time t ce 15 30 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characte rization, not 100% tested in production. 3. only applicable as a constraint for a write stat us register instruction when srp0 is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed.
w25q32v - 52 - 11.8 serial output timing 11.9 input timing 11.10 hold timing
w25q32v publication release date: august 19, 2009 - 53 - preliminary - revision e 12. package specification 12.1 8-pin soic 208-mil (package code ss) millimeters inches symbol min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y - - 0.010 - - 0.004 0 - 8 0 - 8 notes: 1. controlling dimensions: millimeter s, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e1 do not include mold flash protrusions and should be meas ured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
w25q32v - 54 - 12.2 8-contact 6x5mm wson (package code zp) ? millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.0275 0.0295 0.0314 a1 0.00 0.02 0.05 0.0000 0.0007 0.0019 b 0.35 0.40 0.48 0.0137 0.0157 0.0188 c - 0.20 ref. - - 0.0078 ref. - d 5.90 6.00 6.10 0.2322 0.2362 0.2401 d2 3.35 3.40 3.45 0.1318 0.1338 0.1358 e 4.90 5.00 5.10 0.1929 0.1968 0.2007 e2 4.25 4.30 4.35 0.1673 0.1692 0.1712 e (2) 1.27 bsc 0.0500 bsc l 0.55 0.60 0.65 0.0216 0.0236 0.0255 y 0.00 - 0.75 0.0000 - 0.0029
w25q32v publication release date: august 19, 2009 - 55 - preliminary - revision e 8-contact 6x5mm wson cont?d. millimeters inches symbol min typ. max min typ. max solder pattern m 3.40 0.1338 n 4.30 0.1692 p 6.00 0.2360 q 0.50 0.0196 r 0.75 0.0255 notes: 1. advanced packaging information; please contact winbond for the latest minimum and maximum specifications. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusi ons and should be measured from the bottom of the package. 4. the metal pad area on the bottom c enter of the package is connected to the device ground (gnd pin). avoid placement of exposed pc b vias under the pad.
w25q32v - 56 - 12.3 8-contact 8x6mm wson (package code ze) millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.02755 0.02952 0.03149 a1 0.00 0.02 0.05 0.0000 0.00078 0.00196 b 0.35 0.40 0.48 0.01377 0.01574 0.01889 c 0.19 .0.20 0.25 0.00748 0.00787 0.00984 d 7.90 8.00 8.10 0.31102 0.31496 0.31889 d2 4.60 4.65 4.70 0.18110 0.18307 0.18503 e 5.90 6.00 6.10 0.23228 0.23622 0.24015 e2 5.15 5.20 5.25 0.20275 0.20472 0.20669 e 1.27 bsc 0.05000 bsc l 0.45 0.50 0.55 0.01771 0.01968 0.02165
w25q32v publication release date: august 19, 2009 - 57 - preliminary - revision e 12.4 16-pin soic 300-mil (package code sf) millimeters inches symbol min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 - 0.30 0.004 - 0.012 a2 - 2.31 - - 0.091 - b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e1 7.39 7.49 7.59 0.291 0.295 0.299 e 2 1.27 bsc 0.50 bsc l 0.38 0.81 1.27 0.015 0.032 0.050 y - - 0.076 - - 0.003 0 - 8 0 - 8 notes: 1. controlling dimensions: inches , unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusi ons and should be measured from the bottom of the package.
w25q32v - 58 - 13. ordering information (1) w 25q xx v xx (1) (2) i = industrial (-40c to +85c) ss = 8-pin soic 208-mil zp = 8-pad wson 6x5mm sf = 16-pin soic 300-mil ze = 8-pad wson 8x6mm v = 2.7v to 3.6v 32 = 32m-bit 25q = spiflash serial flash memo ry with 4kb sectors, dual/quad i/o w = winbond g = green package (lead-free, rohs compliant, halogen-free (tbba), antimony-oxide-free sb 2 o 3 ) notes: 1a. only the 2 nd letter is used for the part marking; wson pa ckage type zp is not used for the part marking. 1b. the ?w? prefix is not included on the part marking. 2a. standard bulk shipments are in tube (shape e). please specif y alternate packing method, such as tape and reel (shape t) or tray (shape s), when placing orders. 2b. for shipments with otp feature enabl ed, please specify when placing orders.
w25q32v publication release date: august 19, 2009 - 59 - preliminary - revision e 13.1 valid part numbers and top side marking the following table provides the valid part numbers for the w25q32v spiflash memory. please contact winbond for specific availability by density and pa ckage type. winbond spiflash memories use an 11- digit product number for ordering. however, due to limited space, the top side marking on all packages use an abbreviated 9-digit number. package type density product number top side marking ss soic-8 208mil 32m-bit w25q32vssig 25q32vsig sf soic-16 300mil 32m-bit w25q32vsfig 25q32vfig zp (1) wson-8 6x5mm 32m-bit w25q32vzpig 25q32vig ze (1)(2) wson-8 8x6mm 32m-bit W25Q32VZEIG 25q32vig note: 1. wson package type zp is not used in the top side marking. 2. this package type is a special order, please contact winbond for ordering information.
w25q32v - 60 - 14. revision history version date page description a 10/20/06 new create advanced a1 11/9/06 various figures 2, 3a-b, 13a?14c, 16, 24, 25 table 10.2.2: write status reg 1 and 2 erase suspend 10.2.21 tchsh, tshch = 5ns a2 11/15/06 49 tshsl = 10ns for read & 50ns for write, erase and program instructions a3 2/22/07 20, 45, 49 & 57 removed octal word read quad i/o instruction. updated ordering information. added transient voltage specification. a4 4/20/07 19, 28, 30 & 45 added mode bi t reset instruction and description. a5 6/20/07 13, 15-17 & 23 added note for srp1,0 status during power lock- down protection. updated status register memory protection tables. b 9/26/07 5, 11, 13, 15-17, 19, 35, 36, 43, 45-47, 50 & 59 updated instruction diagrams. updated status register memory protection tables. added note for power lock-down, otp functions. added note for 64 bit unique id. added note for 32kb/64kb block erase command. updated mode bit reset command description. updated data retention temperature. updated tshsl description, added tclqv2. updated tbp1. c 8/24/08 5, 18, 26, 28, 30, 31, 40, 45, 46, 50, 51, 57 & 58 separated w25q16 & w25q32. updated features section. added octal word read quad i/o (e3h) instruction. added note for hpm release (06h & b9h). added 60mhz clock frequency f r1 . updated continuous read mode descriptions. updated tclh, tcll. updated erase time. updated top side marking table. added note for wson top side marking. d 12/19/08 03/12/09 03/13/09 5,17,26,28,30,40, 41,48 46 50 57 58 5 13 removed high performance mode (hpm) removed commercial removed ac parameters f r2 updated ordering information diagram updated part number table change 5ma to 4ma typo qe pin to qe bit
w25q32v publication release date: august 19, 2009 - 61 - preliminary - revision e revision history (cont) version date page description e 08/19/09 5,6,8 38,39,43 54~57,61 erase suspend/resume description update added wson 8x6-mm package(special order) package diagrams updated uid waveform diagram updated preliminary designation the ?preliminary? designation on a winbond spiflash memory datasheet indicates that the product is not fully characterized. the specifications are subject to change and are not guaranteed. winbond or an authorized sales representative should be consulted fo r current information before using this product. trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical impl antation, atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, com bustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales .

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